135 search results - page 9 / 27 » Reducing Power Dissipation in SRAM during Test |
VTS
2008
IEEE
14 years 2 months ago
2008
IEEE
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
VTS
2002
IEEE
14 years 16 days ago
2002
IEEE
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
ATS
2005
IEEE
14 years 1 months ago
2005
IEEE
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
FPGA
2003
ACM
14 years 26 days ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...