293 search results - page 18 / 59 » Reducing Power with Performance Constraints for Parallel Spa... |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—In embedded computing we face a continuously growing algorithm complexity combined with a constantly rising number of applications running on a single system. Multi-core systems...
IPPS
1998
IEEE
13 years 12 months ago
1998
IEEE
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
ICCD
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...