221 search results - page 38 / 45 » Reducing the Interconnection Network Cost of Chip Multiproce... |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Memory and communication architectures have a significant impact on the cost, performance, and time-to-market of complex multi-processor system-on-chip (MPSoC) designs. The memory...
CASES
2009
ACM
14 years 2 months ago
2009
ACM
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...
ICCD
2002
IEEE
14 years 4 months ago
2002
IEEE
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applicati...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
ISCA
2008
IEEE
13 years 7 months ago
2008
IEEE
Evolving technology and increasing pin-bandwidth motivate the use of high-radix routers to reduce the diameter, latency, and cost of interconnection networks. High-radix networks,...