49 search results - page 4 / 10 » Reduction of Power Dissipation during Scan Testing by Test V... |
VTS
2002
IEEE
14 years 13 days ago
2002
IEEE
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
ICES
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional precharge activity is not necessary during test mode because of the predictable a...
ETS
2009
IEEE
13 years 5 months ago
2009
IEEE
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
VTS
2002
IEEE
14 years 13 days ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...