73 search results - page 14 / 15 » Reduction of interpolants for logic synthesis |
GLVLSI
2011
IEEE
12 years 11 months ago
2011
IEEE
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subt...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
IOLTS
2009
IEEE
14 years 2 months ago
2009
IEEE
— The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault toleran...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Functional unit shutdown based on MTCMOS devices is effective for leakage reduction in aggressively scaled technologies. However, the applicability of MTCMOS-based shutdown in a s...
ASAP
2005
IEEE
14 years 1 months ago
2005
IEEE
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...