76 search results - page 5 / 16 » Register placement for low power clock network |
TVLSI
2010
13 years 2 months ago
2010
This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture--Signal processi...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
VLSID
2007
IEEE
14 years 1 months ago
2007
IEEE
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...