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DAC
2006
ACM
14 years 10 months ago
Criticality computation in parameterized statistical timing
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswa...
DAC
2010
ACM
14 years 28 days ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
13 years 7 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...
ICPR
2004
IEEE
14 years 10 months ago
From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
Jie Han, Pieter Jonker
SEUS
2010
IEEE
13 years 6 months ago
Ubiquitous Verification of Ubiquitous Systems
Abstract. Ubiquitous embedded computing systems expected to reliably perform one or more relevant tasks need design and verification methods currently not available. New envisioned...
Reinhard Wilhelm, Matteo Maffei