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ICES
2003
Springer
165views Hardware» more  ICES 2003»
14 years 21 days ago
Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms
This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor r...
Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Me...
ICASSP
2011
IEEE
12 years 11 months ago
Hardware acceleration of iterative image reconstruction for X-ray computed tomography
X-ray computed tomography (CT) images could be improved using iterative image reconstruction if the 3D conebeam forward- and back-projection computations can be accelerated signif...
Jung Kuk Kim, Zhengya Zhang, Jeffrey A. Fessler
FCCM
2008
IEEE
162views VLSI» more  FCCM 2008»
14 years 1 months ago
Multiobjective Optimization of FPGA-Based Medical Image Registration
With a multitude of technological innovations, one emerging trend in image processing, and medical image processing, in particular, is custom hardware implementation of computatio...
Omkar Dandekar, William Plishker, Shuvra S. Bhatta...
DSD
2004
IEEE
122views Hardware» more  DSD 2004»
13 years 11 months ago
On the Packet-Switched Implementation of a Discrete-Time CNN
Cellular Neural Networks are widely used with real-time image processing's applications. Such systems can be efficiently realized using macro enriched fieldprogrammable gate-...
Suleyman Malki, Lambert Spaanenburg
JSAC
2006
165views more  JSAC 2006»
13 years 7 months ago
Image-Based Anomaly Detection Technique: Algorithm, Implementation and Effectiveness
The frequent and large-scale network attacks have led to an increased need for developing techniques for analyzing network traffic. This paper presents NetViewer, a network measure...
Seong Soo Kim, A. L. Narasimha Reddy