70 search results - page 5 / 14 » Retargetable Cache Simulation Using High Level Processor Mod... |
RTCSA
2007
IEEE
14 years 1 months ago
2007
IEEE
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
PLDI
1995
ACM
13 years 11 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
DSRT
2009
IEEE
13 years 11 months ago
2009
IEEE
The recent emergence of dramatically large computational power, spanning desktops with multicore processors and multiple graphics cards to supercomputers with 105 processor cores,...
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...