57 search results - page 3 / 12 » Retiming and clock scheduling for digital circuit optimizati... |
DAC
1996
ACM
13 years 11 months ago
1996
ACM
1- A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This met...
ASPDAC
2009
ACM
14 years 1 months ago
2009
ACM
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Process variations in digital circuits make sequential circuit timing validation an extremely challenging task. In this paper, a Statistical Bellman-Ford (SBF) algorithm is pro...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...