57 search results - page 5 / 12 » Retiming and clock scheduling for digital circuit optimizati... |
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
This paper considers the problem of determining an optimal clock skew schedule for a synchronous VLSI circuit. A novel formulation of clock skew scheduling as a constrained quadrat...
ASPDAC
2005
ACM
13 years 11 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
ICCAD
2009
IEEE
13 years 7 months ago
2009
IEEE
Clock skew scheduling has been effectively used to reduce the clock period of sequential circuits. However, this technique may become impractical if a different skew must be appli...
DATE
1997
IEEE
14 years 2 months ago
1997
IEEE
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...
ICCAD
1997
IEEE
14 years 1 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...