60 search results - page 6 / 12 » Retiming with Interconnect and Gate Delay |
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
VLSID
1999
IEEE
13 years 12 months ago
1999
IEEE
We describe an improved iterationless approach for computing the effective capacitance of an interconnect load at a driving gate output. The speed and accuracy of our approach mak...
ICCAD
1998
IEEE
13 years 12 months ago
1998
IEEE
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
IPPS
2002
IEEE
14 years 19 days ago
2002
IEEE
In the sub-micron technology era, wire delays are becoming much more important than gate delays, making it particularly attractive to go for clustered designs. A common form of cl...
ISQED
2003
IEEE
14 years 1 months ago
2003
IEEE
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...