2778 search results - page 28 / 556 » Reuse Technique in Hardware Design |
154
click to vote
ITC
1995
IEEE
15 years 9 months ago
1995
IEEE
An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25k gate CMOS Test Chip has been designed, manufac...
119
click to vote
ISCAS
2008
IEEE
16 years 20 hour ago
2008
IEEE
— This paper proposes a multiple-divide technique using by-2, by-3, and by-4 frequency dividers to realize a lower phase-noise LC-VCO, and explores the design space of low-phasen...
117
click to vote
ASAP
2007
IEEE
15 years 12 months ago
2007
IEEE
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754)....
176
click to vote
ISQED
2010
IEEE
15 years 7 months ago
2010
IEEE
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
154
Voted
SIGSOFT
2005
ACM
15 years 11 months ago
2005
ACM
Reuse has always been a major goal in software engineering, since it promises large gains in productivity, quality and time to market reduction. Practical experience has shown tha...