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» Reuse Technique in Hardware Design
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FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
14 years 2 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
ACMMSP
2004
ACM
125views Hardware» more  ACMMSP 2004»
14 years 1 months ago
Improving trace cache hit rates using the sliding window fill mechanism and fill select table
As superscalar processors become increasingly wide, it is inevitable that the large set of instructions to be fetched every cycle will span multiple noncontiguous basic blocks. Th...
Muhammad Shaaban, Edward Mulrane
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
14 years 1 months ago
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
Yi-Hui Cheng, Yao-Wen Chang
ISER
2004
Springer
123views Robotics» more  ISER 2004»
14 years 1 months ago
Free-Climbing with a Multi-Use Robot
This paper presents a new four-limbed robot, LEMUR IIb (Legged Excursion Mechanical Utility Rover), that can free-climb vertical rock surfaces. This robot was designed to have a nu...
Timothy Bretl, Stephen M. Rock, Jean-Claude Latomb...
ICPP
2003
IEEE
14 years 1 months ago
Enabling Partial Cache Line Prefetching Through Data Compression
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
Youtao Zhang, Rajiv Gupta