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» Reuse in the application layer
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114
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VLSID
2002
IEEE
159views VLSI» more  VLSID 2002»
16 years 4 months ago
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...
131
Voted
HPCA
2005
IEEE
16 years 4 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...
210
Voted
SIGMOD
2009
ACM
139views Database» more  SIGMOD 2009»
16 years 3 months ago
Detecting and resolving unsound workflow views for correct provenance analysis
views abstract groups of tasks in a workflow into high level composite tasks, in order to reuse sub-workflows and facilitate provenance analysis. However, unless a view is careful...
Peng Sun, Ziyang Liu, Susan B. Davidson, Yi Chen
130
Voted
WISE
2009
Springer
16 years 25 days ago
Spectral Clustering in Social-Tagging Systems
Social tagging is an increasingly popular phenomenon with substantial impact on the way we perceive and understand the Web. For the many Web resources that are not self-descriptive...
Alexandros Nanopoulos, Hans-Henning Gabriel, Myra ...
138
Voted
ICCD
2003
IEEE
123views Hardware» more  ICCD 2003»
16 years 18 days ago
Simplifying SoC design with the Customizable Control Processor Platform
With the circuit density available in today’s ASIC design systems, increased integration is possible creating more complexity in the design of a System on a Chip (SoC). IBM’s ...
C. Ross Ogilvie, Richard Ray, Robert Devins, Mark ...