167 search results - page 12 / 34 » Robust Techniques for Watermarking Sequential Circuit Design... |
ICCAD
1996
IEEE
13 years 11 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
—Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pip...
IH
1998
Springer
13 years 11 months ago
1998
Springer
Advanced CAD tools and high-density VLSI technologies have combined to create a new market for reusable digital designs. The economic viability of the new core-based design paradig...
ISQED
2006
IEEE
14 years 1 months ago
2006
IEEE
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...