768 search results - page 30 / 154 » Robustness of Sequential Circuits |
VTS
2000
IEEE
14 years 1 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
ICCAD
1995
IEEE
14 years 13 days ago
1995
IEEE
This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
UAI
2008
13 years 10 months ago
2008
Decision circuits have been developed to perform efficient evaluation of influence diagrams [Bhattacharjya and Shachter, 2007], building on the advances in arithmetic circuits for...
ASPDAC
2007
ACM
14 years 27 days ago
2007
ACM
Abstract-- In this paper we present the Statistical Retimingbased Timing Analysis (SRTA) algorithm. The goal is to compute the timing slack distribution for the nodes in the timing...
ICCAD
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents ISCLEs, a novel and robust analog design method that promises to scale with Moore’s Law, by doing boosting-style importance sampling on digital-sized circuit...