768 search results - page 32 / 154 » Robustness of Sequential Circuits |
EURODAC
1995
IEEE
14 years 13 days ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
DATE
1998
IEEE
14 years 1 months ago
1998
IEEE
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...
ATS
2000
IEEE
14 years 1 months ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
Limited Switch Dynamic Logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primar...
FMCAD
2009
Springer
14 years 3 months ago
2009
Springer
— There is a long history of investigations and debates on whether a sequence of retiming and resynthesis is complete for all sequential transformations (on steady states). It ha...