Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
1 — This paper presents a new design automation tool based on a modified genetic algorithm kernel, in order to increase efficiency on the analog circuit and system design cycle. ...
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic b...
Helmut E. Graeb, Stephan Zizala, Josef Eckmueller,...