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SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
14 years 2 months ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...
ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 6 months ago
Statistical timing verification for transparently latched circuits through structural graph traversal
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
Xingliang Yuan, Jia Wang
INTEGRATION
2010
172views more  INTEGRATION 2010»
13 years 7 months ago
Analog circuits optimization based on evolutionary computation techniques
1 — This paper presents a new design automation tool based on a modified genetic algorithm kernel, in order to increase efficiency on the analog circuit and system design cycle. ...
Manuel F. M. Barros, Jorge Guilherme, Nuno Horta
DAC
2005
ACM
14 years 9 months ago
Robust gate sizing by geometric programming
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
ICCAD
2001
IEEE
153views Hardware» more  ICCAD 2001»
14 years 5 months ago
The Sizing Rules Method for Analog Integrated Circuit Design
This paper presents the sizing rules method for analog CMOS circuit design that consists of: first, the development of a hierarchical library of transistor pair groups as basic b...
Helmut E. Graeb, Stephan Zizala, Josef Eckmueller,...