768 search results - page 6 / 154 » Robustness of Sequential Circuits |
DSN
2003
IEEE
14 years 22 days ago
2003
IEEE
This paper describes the design and evaluation of a robust integrator for software-implemented control systems. The integrator is constructed as a generic component in the Simulin...
ASPDAC
2000
ACM
13 years 11 months ago
2000
ACM
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
FMCAD
2004
Springer
14 years 25 days ago
2004
Springer
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
JISE
2000
13 years 7 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper presents new test generation techniques for improving the average-case performance of the iterative logic array based deterministic sequential circuit test generation a...