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DAC
2004
ACM
14 years 9 months ago
Post-layout logic optimization of domino circuits
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
Aiqun Cao, Cheng-Kok Koh
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
14 years 3 months ago
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits
Metallic Carbon Nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs), causing excessive leakage, degraded noise margin and delay variat...
Jie Zhang, Nishant Patil, Subhasish Mitra
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
14 years 10 days ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
APIN
2002
121views more  APIN 2002»
13 years 8 months ago
Applying Learning by Examples for Digital Design Automation
This paper describes a new learning by example mechanism and its application for digital circuit design automation. This mechanism uses finite state machines to represent the infer...
Ben Choi
DATE
2007
IEEE
89views Hardware» more  DATE 2007»
14 years 3 months ago
Computing synchronizer failure probabilities
— System-on-Chip designs often have a large number of timing domains. Communication between these domains requires synchronization, and the failure probabilities of these synchro...
Suwen Yang, Mark R. Greenstreet