768 search results - page 8 / 154 » Robustness of Sequential Circuits |
DFT
2003
IEEE
14 years 22 days ago
2003
IEEE
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
DAC
1991
ACM
13 years 11 months ago
1991
ACM
-Conventionallyself-test hardware is added after synthesis is completed. For highly sequential circuits like controllersthis design method eitherleads to high hardware overheadsor ...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
Abstract A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences t...
ICCD
1997
IEEE
13 years 11 months ago
1997
IEEE
Abstract— In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock perio...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...