59 search results - page 9 / 12 » Runtime leakage power estimation technique for combinational... |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
In this paper, we propose a new technique for the combined voltage scaling of processors and communication links, taking into account dynamic as well as leakage power consumption....
VLSID
2007
IEEE
14 years 7 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes two techniques to quantify energy consumption of burst-modeasynchronous(clock-less)controlcircuits. The circuit specifications consideredare extended burst-m...