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DATE
2003
IEEE
98views Hardware» more  DATE 2003»
14 years 1 months ago
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as...
Abhik Roychoudhury, Tulika Mitra, S. R. Karri
DAC
2004
ACM
14 years 9 months ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...
DATE
1998
IEEE
108views Hardware» more  DATE 1998»
14 years 6 days ago
Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor
The demands in terms of processing performance, communication bandwidth and real-time throughput of many multimedia applications are much higher than today's processing archi...
Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin...
SPIESR
1996
118views Database» more  SPIESR 1996»
13 years 9 months ago
Performances of Multiprocessor Multidisk Architectures for Continuous Media Storage
Multimedia interfaces increase the need for large image databases, capable of storing and reading streams of data with strict synchronicity and isochronicity requirements. In orde...
Benoit A. Gennart, Vincent Messerli, Roger D. Hers...
DAC
2003
ACM
14 years 1 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III