Sciweavers

103 search results - page 20 / 21
» SEU tolerant device, circuit and processor design
Sort
View
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 4 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 3 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 3 months ago
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration
attributed to the high regularity of memories, PAs and FPGAs, and the ease with which they can be tested and reconfigured to avoid faulty elements. Digital microfluidicsbased bioch...
Fei Su, Krishnendu Chakrabarty, Vamsee K. Pamula
CASES
2006
ACM
14 years 1 months ago
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety c...
Jason A. Blome, Shantanu Gupta, Shuguang Feng, Sco...
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
14 years 1 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...