202 search results - page 4 / 41 » SOC Test Scheduling Using Simulated Annealing |
CPHYSICS
2006
13 years 7 months ago
2006
A modification of the standard Simulated Annealing (SA) algorithm is presented for finding the global minimum of a continuous multidimensional, multimodal function. We report resu...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
DSD
2009
IEEE
14 years 2 months ago
2009
IEEE
—Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating duri...