The purpose of this paper is to develop a exible design for test methodology for testing a core-based system on chip SOC. The novel feature of the approach is the use an embedde...
Christos A. Papachristou, F. Martin, Mehrdad Noura...
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
Test data compression (TDC) is a promising low-cost methodology for System-on-a-Chip (SOC) test. This is due to the fact that it can reduce not only the volume of test data but al...
Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola N...
In a carefully structured study spanning several months, the authors visited numerous companies focused on Design For Test methodologies in SoC Test, Characterization, and Failure...
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...