97 search results - page 9 / 20 » SRAM Cell Current in Low Leakage Design |
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
TheRFdesignparadigm will changesignificantly asCMOS technology scales and integration levels rise to accommodate multi-band, multi-mode transceivers and baseband processors. This...