2020 search results - page 31 / 404 » Scalable Instruction-Level Parallelism. |
HPCA
2006
IEEE
14 years 9 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
ICCD
2004
IEEE
14 years 5 months ago
2004
IEEE
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
RTAS
2008
IEEE
14 years 3 months ago
2008
IEEE
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
MICRO
2006
IEEE
14 years 2 months ago
2006
IEEE
The superblock is a scheduling region which exposes instruction level parallelism beyond the basic block through speculative execution of instructions. In general, scheduling supe...
ASPDAC
2004
ACM
14 years 2 months ago
2004
ACM
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...