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ISCA
1998
IEEE
134views Hardware» more  ISCA 1998»
14 years 1 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
Stephen W. Keckler, William J. Dally, Daniel Maski...
IFIPPACT
1994
13 years 10 months ago
Microcode Generation for Flexible Parallel Target Architectures
: Advanced architectural features of microprocessors like instruction level parallelism and pipelined functional hardware units require code generation techniques beyond the scope ...
Rainer Leupers, Wolfgang Schenk, Peter Marwedel
DATE
2005
IEEE
113views Hardware» more  DATE 2005»
14 years 2 months ago
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda...
EUROPAR
1997
Springer
14 years 29 days ago
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors
The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that...
Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, K...
TVCG
2012
210views Hardware» more  TVCG 2012»
11 years 11 months ago
Scalable Multivariate Volume Visualization and Analysis Based on Dimension Projection and Parallel Coordinates
—In this paper, we present an effective and scalable system for multivariate volume data visualization and analysis with a novel transfer function interface design that tightly c...
Hanqi Guo, He Xiao, Xiaoru Yuan