22 search results - page 2 / 5 » Scalable Test Generators for High-Speed Datapath Circuits |
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
Test model generation is crucial in the test generation process of a high-performance design targeted for large volume production. A key process in test model generation requires ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
Commercial tools for standard-cell based datapath design are here classed according to design flows, and the advantages of each class are discussed with the results of two test ci...