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» Scale in Chip Interconnect requires Network Technology
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DAC
2002
ACM
14 years 8 months ago
The next chip challenge: effective methods for viable mixed technology SoCs
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
H. Bernhard Pogge
CORR
2008
Springer
92views Education» more  CORR 2008»
13 years 7 months ago
Interconnect Challenges in Highly Integrated MEMS/ASIC Subsystems
Micromechanical devices like accelerometers or rotation sensors form an increasing segment beneath the devices supplying the consumer market. A hybrid integration approach to buil...
N. Marenco, S. Warnat, W. Reinert
ANCS
2009
ACM
13 years 5 months ago
Design of a scalable nanophotonic interconnect for future multicores
As communication-centric computing paradigm gathers momentum due to increased wire delays and excess power dissipation with technology scaling, researchers have focused their atte...
Avinash Karanth Kodi, Randy Morris
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 1 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
ISCA
2005
IEEE
147views Hardware» more  ISCA 2005»
14 years 1 months ago
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen