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ISCA
2010
IEEE
340views Hardware» more  ISCA 2010»
14 years 15 days ago
Necromancer: enhancing system throughput by animating dead cores
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
12 years 11 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
FPL
2006
Springer
99views Hardware» more  FPL 2006»
13 years 11 months ago
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This techniques can be used to identify registered cores for IP ...
Daniel Ziener, Stefan Assmus, Jürgen Teich
ICCD
2006
IEEE
185views Hardware» more  ICCD 2006»
14 years 4 months ago
An accurate Energy estimation framework for VLIW Processor Cores
— In this paper, we present a comprehensive energy estimation framework for software executing on Very Long Instruction Word (VLIW) processor cores. The proposed energy model is ...
Sourav Roy, Rajat Bhatia, Ashish Mathur
FAST
2011
12 years 11 months ago
FastScale: Accelerate RAID Scaling by Minimizing Data Migration
Previous approaches to RAID scaling either require a very large amount of data to be migrated, or cannot tolerate multiple disk additions without resulting in disk imbalance. In t...
Weimin Zheng, Guangyan Zhang