86 search results - page 11 / 18 » Scaling and Packing on a Chip Multiprocessor |
MICRO
2007
IEEE
14 years 4 months ago
2007
IEEE
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
TPDS
2008
13 years 9 months ago
2008
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
GLVLSI
2009
IEEE
14 years 5 months ago
2009
IEEE
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
HPCA
2007
IEEE
14 years 10 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
HPCA
2003
IEEE
14 years 10 months ago
2003
IEEE
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...