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» Scan chain clustering for test power reduction
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ATS
2005
IEEE
118views Hardware» more  ATS 2005»
14 years 1 months ago
Partial Gating Optimization for Power Reduction During Test Application
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ra...
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
14 years 4 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
VTS
2003
IEEE
122views Hardware» more  VTS 2003»
14 years 27 days ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 1 months ago
Two efficient methods to reduce power and testing time
Reducing power dissipation and testing time is accomplished by forming two clusters of don’t-care bit inside an input and a response test cube. New reordering scheme of scan lat...
Il-soo Lee, Tony Ambler