61 search results - page 7 / 13 » Scan chain clustering for test power reduction |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Power dissipation during test is a major challenge in testing integrated circuits. Dynamic power has been the dominant part of power dissipation in CMOS circuits, however, in futu...
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
TVLSI
2010
13 years 2 months ago
2010
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
— In this paper we investigate an effective approach to construct a linear decompression network in the multiple scan chain architecture. A minimal pin architecture, complemented...
ITC
2003
IEEE
14 years 27 days ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...