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CODES
2005
IEEE
14 years 1 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
14 years 1 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
IPPS
2002
IEEE
14 years 22 days ago
Performance Prediction Technology for Agent-Based Resource Management in Grid Environments
Resource management constitutes an important infrastructural component of a computational grid environment. The aim of grid resource management is to efficiently schedule applicat...
Junwei Cao, Stephen A. Jarvis, Daniel P. Spooner, ...
IPPS
2009
IEEE
14 years 2 months ago
Performance projection of HPC applications using SPEC CFP2006 benchmarks
Performance projections of High Performance Computing (HPC) applications onto various hardware platforms are important for hardware vendors and HPC users. The projections aid hard...
Sameh Sharkawi, Don DeSota, Raj Panda, Rajeev Indu...
DAC
2002
ACM
14 years 8 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou