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» Secure Partial Reconfiguration of FPGAs
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IPPS
2007
IEEE
14 years 1 months ago
Distributed IDS using Reconfigurable Hardware
With the rapid growth of computer networks and network infrastructures and increased dependency on the internet to carry out day-to-day activities, it is imperative that the compo...
Ashok Kumar Tummala, Parimal Patel
FPL
2006
Springer
219views Hardware» more  FPL 2006»
13 years 11 months ago
FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously in...
François-Xavier Standaert, Gaël Rouvro...
CODES
2010
IEEE
13 years 4 months ago
Hardware/software optimization of error detection implementation for real-time embedded systems
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...
Adrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izo...
FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
14 years 1 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...
FPL
2008
Springer
105views Hardware» more  FPL 2008»
13 years 9 months ago
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems
A high-speed and secure dynamic partial reconfiguration (DPR) system is realized with AES-GCM that guarantees both confidentiality and authenticity of FPGA bitstreams. In DPR syst...
Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji T...