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FPGA
2005
ACM
137views FPGA» more  FPGA 2005»
14 years 1 months ago
HARP: hard-wired routing pattern FPGAs
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...
Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia...
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 8 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
DELTA
2008
IEEE
14 years 2 months ago
Adaptive Diagnostic Pattern Generation for Scan Chains
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...
Fei Wang, Yu Hu, Xiaowei Li
COCO
2009
Springer
128views Algorithms» more  COCO 2009»
14 years 2 months ago
An Almost Optimal Rank Bound for Depth-3 Identities
—We show that the rank of a depth-3 circuit (over any field) that is simple, minimal and zero is at most O(k3 log d). The previous best rank bound known was 2O(k2 ) (log d)k−2...
Nitin Saxena, C. Seshadhri
3DIC
2009
IEEE
279views Hardware» more  3DIC 2009»
14 years 2 months ago
Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits
Abstract—Modeling parasitic parameters of Through-SiliconVia (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circ...
Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, ...