376 search results - page 57 / 76 » Self-Assembled Circuit Patterns |
Publication
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
The negative effect of electromigration on signal and power line lifetime and functional reliability is an increasingly important problem for the physical design of integrated cir...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
ISCAS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Scaling of CMOS technologies has led to dramatic increase in sub-threshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage. Leakage current has now beco...