376 search results - page 60 / 76 » Self-Assembled Circuit Patterns |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...
ISNN
2005
Springer
14 years 1 months ago
2005
Springer
Built on the theories of biological neural network, artificial neural network methods have shown many significant advantages. However, the memory space in an artificial neural chip...
ITC
2003
IEEE
14 years 24 days ago
2003
IEEE
We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for...
DAC
1996
ACM
13 years 11 months ago
1996
ACM
Accurate power estimation is essential for low power digital CMOS circuit design. Power dissipation is input pattern dependent. To obtain an accurate power estimate, a large input...