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IWANN
1995
Springer
13 years 11 months ago
Test Pattern Generation for Analog Circuits Using Neural Networks and Evolutive Algorithms
This paper presents a comparative analysis of neural networks, simulated annealing, and genetic algorithms in the determination of input patterns for testing analog circuits. The ...
José Luis Bernier, Juan J. Merelo Guerv&oac...
IWANN
2005
Springer
14 years 1 months ago
CMOL CrossNets as Pattern Classifiers
This presentation has two goals: (i) to review the recently suggested concept of bio-inspired CrossNet architectures for future hybrid CMOL VLSI circuits and (ii) to present new re...
Jung Hoon Lee, Konstantin Likharev
DAC
2011
ACM
12 years 7 months ago
Efficient incremental analysis of on-chip power grid via sparse approximation
In this paper, a new sparse approximation technique is proposed for incremental power grid analysis. Our proposed method is motivated by the observation that when a power grid net...
Pei Sun, Xin Li, Ming Yuan Ting
ICCAD
1994
IEEE
112views Hardware» more  ICCAD 1994»
13 years 11 months ago
Selecting partial scan flip-flops for circuit partitioning
This paper presents a new method of selecting scan ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
Toshinobu Ono
DAC
1997
ACM
13 years 11 months ago
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits
This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exerc...
Oriol Roig, Jordi Cortadella, Marco A. Peña...