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ISQED
2009
IEEE
133views Hardware» more  ISQED 2009»
14 years 2 months ago
A novel ACO-based pattern generation for peak power estimation in VLSI circuits
Estimation of maximal power consumption is an essential task in VLSI circuit realizations since power value significantly affects the reliability of the circuits. The key issue o...
Yi-Ling Liu, Chun-Yao Wang, Yung-Chih Chen, Ya-Hsi...
ET
2000
145views more  ET 2000»
13 years 7 months ago
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
Jaan Raik, Raimund Ubar
CP
1998
Springer
13 years 11 months ago
Generation of Test Patterns for Differential Diagnosis of Digital Circuits
In a faulty digital circuit, many (single) faulty gates may explain the observed findings. In this paper we are mostly concerned, not in obtaining alternative diagnoses, but rathe...
Francisco Azevedo, Pedro Barahona
TCS
2002
13 years 7 months ago
Neural circuits for pattern recognition with small total wire length
One of the most basic pattern recognition problems is whether a certain local feature occurs in some linear array to the left of some other local feature. We construct in this art...
Robert A. Legenstein, Wolfgang Maass
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 7 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy