605 search results - page 28 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
DATE
2004
IEEE
2004
IEEE
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
13 years 11 months ago
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
WSC
1997
13 years 8 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
MICRO
1999
IEEE
13 years 11 months ago
1999
IEEE
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a singl...
HPCA
2006
IEEE
14 years 7 months ago
2006
IEEE
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...