605 search results - page 31 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
IEEEPACT
2009
IEEE
14 years 2 months ago
2009
IEEE
With advances in hardware, instruction set architectures are undergoing continual evolution. As a result, compilers are under constant pressure to adapt and take full advantage of...
LCTRTS
2009
Springer
14 years 2 months ago
2009
Springer
Register file (RF) is extremely vulnerable to soft errors, and traditional redundancy based schemes to protect the RF are prohibitive not only because RF is often in the timing c...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
An architectural solution to reducing memory energy consumption is to adopt a multi-bank memory system instead of a monolithic (single-bank) memory system. Some recent multi-bank ...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Extensible processors, which allow customization for an application domain by extending the core instruction set architecture, are becoming increasingly popular for embedded syste...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...