605 search results - page 33 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāspecific operations. We report our experience with Chimae...
ISSS
2002
IEEE
14 years 10 days ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
MICRO
2002
IEEE
14 years 10 days ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
GECCO
2008
Springer
13 years 8 months ago
2008
Springer
The realization of a control unit can be done using a complex circuitry or microprogramming. The latter may be considered as an alternative method of implementation of machine ins...
HPCA
2003
IEEE
14 years 7 months ago
2003
IEEE
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...