605 search results - page 80 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
Clustered ILP processors are characterized by a large number of non-centralized on-chip resources grouped into clusters. Traditional code generation schemes for these processors c...
HPCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper describes a hardware-software co-design approach for flexible programmable Galois Field Processing for applications which require operations over GF(2m ), such as RS an...
DAC
2004
ACM
14 years 7 days ago
2004
ACM
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...