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VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 2 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
HPCA
1999
IEEE
14 years 24 days ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi
IADIS
2004
13 years 10 months ago
Prototype of Cyber Assistant Professor: CAP
To reduce the production cost of 3D-CG educational contents for e-Learning system and to improve the capability of self-learning system, we developed a new self-learning system ba...
Hiroshi Matsuda, Yoshiaki Shindo
ICCAD
1996
IEEE
85views Hardware» more  ICCAD 1996»
14 years 20 days ago
Exploiting regularity for low-power design
Abstract -- Current day behavioral-synthesis techniques produce architectures that are power-inefficient in the interconnect. Experiments have demonstrated that in synthesized desi...
Renu Mehra, Jan M. Rabaey
HPCA
2008
IEEE
14 years 8 months ago
Supporting highly-decoupled thread-level redundancy for parallel programs
The continued scaling of device dimensions and the operating voltage reduces the critical charge and thus natural noise tolerance level of transistors. As a result, circuits can p...
M. Wasiur Rashid, Michael C. Huang