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EURODAC
1995
IEEE
153views VHDL» more  EURODAC 1995»
13 years 11 months ago
VHDL-based communication and synchronization synthesis
This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level descripti...
Wolfgang Ecker, Manfred Huber
VLSID
2002
IEEE
105views VLSI» more  VLSID 2002»
14 years 8 months ago
A Heuristic for Clock Selection in High-Level Synthesis
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahm...
SIAMCO
2002
81views more  SIAMCO 2002»
13 years 7 months ago
Robust Controller Synthesis for Uncertain Time-Varying Systems
In this paper we develop and present new convex synthesis conditions for robust performance in linear time-varying systems, subject to time-varying perturbations. In particular, th...
Carol Pirie, Geir E. Dullerud
CODES
1997
IEEE
14 years 7 days ago
Software Architecture Synthesis for Retargetable Real-time Embedded Systems
– Retargetability of embedded system descriptions not only enables better exploration of the design space and evaluation of cost/performance tradeoffs but also enhances design ma...
Pai H. Chou, Gaetano Borriello
ASPDAC
1995
ACM
116views Hardware» more  ASPDAC 1995»
13 years 11 months ago
A datapath synthesis system for the reconfigurable datapath architecture
Abstract — A datapath synthesis system (DPSS) for the reconfigurable datapath architecture (rDPA) is presented. The DPSS allows automatic mapping of high level descriptions onto...
Reiner W. Hartenstein, Rainer Kress