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LCTRTS
2007
Springer
14 years 2 months ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
Hansu Cho, Samar Abdi, Daniel Gajski
DATE
2009
IEEE
112views Hardware» more  DATE 2009»
14 years 2 months ago
Algebraic techniques to enhance common sub-expression elimination for polynomial system synthesis
: Common sub-expression elimination (CSE) serves as a useful optimization technique in the synthesis of arithmetic datapaths described at RTL. However, CSE has a limited potential ...
Sivaram Gopalakrishnan, Priyank Kalla
ICCAD
1997
IEEE
86views Hardware» more  ICCAD 1997»
14 years 9 days ago
Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems
- Task preemption is a critical enabling mechanism in multi-task VLSI systems. On preemption, data in the register les must be preserved in order for the task to be resumed. This e...
Kyosun Kim, Ramesh Karri, Miodrag Potkonjak
ICCAD
1994
IEEE
127views Hardware» more  ICCAD 1994»
14 years 6 days ago
Synthesis of concurrent system interface modules with automatic protocol conversion generation
-- We describe a new high-level compiler called Integral fordesigning system interface modules. The inputis a high-levelconcurrent algorithmic specification that can model complex ...
Bill Lin, Steven Vercauteren
WSC
2008
13 years 10 months ago
Distributed multi-layered workload synthesis for testing stream processing systems
Testing and benchmarking of stream processing systems requires workload representative of real world scenarios with myriad of users, interacting through different applications ove...
Eric Bouillet, Parijat Dube, David George, Zhen Li...